1. Field of the Invention
The present invention relates to a differential amplifier that can be used as an input buffer.
2. Description of Related Art
Data rates of communication busses continually increase with each new generation of processors. Present computer designs include a bus data rate of approximately 500 megabits per second (Mbits/sec). Data rates of 500 Mbits/sec are difficult to achieve using standard circuit designs because of the parasitic capacitance of the bus board. To overcome the physical limitations of the board, systems of such speed are typically designed to have a low voltage swing (the difference in voltage between a binary "1" and a binary "0"). The low voltage swing can be on the order of 600mV peak to peak.
Most memory and logic circuits operate in the 2-5 V range. Utilizing a high speed/low voltage swing bus with conventional electronic devices, typically requires an input buffer to increase the voltage of the signal from the bus to the devices.
Input buffers of the prior art have often incorporated a differential amplifier which amplifies the difference between the signal and a reference voltage. Most differential amplifier designs are particularly sensitive to fluctuations in temperature or voltages. Variations in the temperature or voltages, can lead to errors in the switching of the amplifier.
U.S. Pat. No. 4,937,476 issued to Bazes discloses an input buffer that utilizes a self-biased differential amplifier. The differential amplifier has a first pair of complementary n and p type FETs coupled to the input signal, and a second pair of complementary n and p type FETs coupled to a reference voltage. The first and second pair of FETs are coupled to a supply voltage that is controlled by a third pair of complementary FETs. The drain pins of the first set of FETs are connected to the gates of the third set of FETs, to create a negative feedback within the amplifier. The bias voltage of the first FETs is set at the midpoint of the active region. If the bias voltage moves from the midpoint, the feedback from the first FETs to the third FETs will vary the supply voltage so that the bias voltage is returned to the center of the active region. Any variations in temperature or voltage are therefore compensated through the self-biasing scheme incorporated into the Bazes design.
To provide an input buffer that can operate at high frequencies, it is desirable to minimize the propagation delays and increase the slew rate of the buffer. Additionally, the propagation delay from the high to low voltage swing is typically different from the propagation delay between the low to high voltage swing. The designer must typically compensate for the skew between the propagation delays. Although the Bazes circuit provides a self-biasing feature, the slew rate and skew between the propagation delays for the Bazes differential amplifier is somewhat unacceptable for usage with a data rate on the order of 500 Mbits/sec. It would therefore be desirable to have a circuit which can provide an input buffer that has an increased slew rate and minimal propagational skew, so that the circuit can be used with a high speed/low voltage swing bus.